The present invention relates to a semiconductor memory such as a mask ROM (read only memory), and more specifically to a mask ROM having an improved cell layout which can minimize an influence of implanted code ions to an adjacent cell.
The mask ROM can be explained to be a ROM which was written with a predetermined content by utilizing a mask pattern in the course of an IC (integrated circuit) fabricating process.
In this mask ROM, a read-out data is generally handled as data having two values, namely, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. These two values are expressed as an on-bit and an off-bit in a flat cell type ROM. On the other hand, considering a threshold of a memory cell transistor, the on-bit and the off-bit are represented by a transistor having a low threshold and a transistor having a high threshold, respectively.
As a method for forming the low-threshold transistor and the high-threshold transistor, distinguishably from each other, the flat cell type ROM includes a method for selectively implanting boron, as an ion implantation impurity, in accordance with a content that is to be written in a mask ROM in the course of the IC fabricating process. This ion implantation is called a xe2x80x9ccode ion implantationxe2x80x9d in the field of the ROM.
Japanese Patent Application Pre-examination Publication No. JP-A61-288464 discloses one example of a cell layout of the flat cell type ROM which was fabricated in accordance with the method capable of forming the low-threshold transistor and the high-threshold transistor, distinguishably from each other. Now, the prior art disclosed by JP-A61-288464 will be described with reference to FIGS. 5 to 8.
FIG. 5 is a diagrammatic plan view for illustrating the cell layout in accordance with the prior art, and FIG. 6 is a diagrammatic sectional view taken along the line Axe2x80x94A in FIG. 5.
As shown in FIGS. 5 and 6, in the prior art, a plurality of bit lines 1, which become a source region and a drain region of memory cell transistors, are formed of N-type diffused regions 1A which are formed in a principal surface of a semiconductor substrate 5 to extend in parallel to one another, separately from one another. A plurality of word lines 2 are formed on an insulating film 6A formed on the principal surface of a semiconductor substrate 5, to extend in parallel to one another, separately from one another, and orthogonally to the bit lines. This arrangement is a so-called flat cell.
In a flat cell ROM fabricating process, after a gate electrode constituting each word line 2 is formed, a P-type impurity is ion-implanted for a device isolation so that a P-type impurity diffused region (not shown in FIG. 6) is formed. Furthermore, an oxide film 6 is deposited to form an interlayer insulator film which covers the word lines 2 and the semiconductor substrate. Thereafter, a photolithography step is carried out for depositing a photoresist 4 for a ROM coding. Thus, the flat cell having the sectional structure shown in FIG. 6 is obtained.
In this condition, code ion implanting openings 3 formed in the photoresist 4 are designed in the prior art to have the same width as a channel width of the memory cell transistor, as shown in FIG. 5. However, since the code ion implantation is carried out after the interlayer insulator film 5 was formed, the energy required for the code ion implantation becomes high.
For example, in the case that a gate polycide constituting the word lines 2 is formed of a polysilicon of 0.1 xcexcm thickness and a tungsten silicide of 0.15 xcexcm thickness, and an interlayer film has a thickness of 0.3 xcexcm to 0.4 xcexcm, when boron is used a dopant, the code ion implantation requires an energy as high as 200 keV to 350 keV.
Therefore, if the code ion implantation is carried out using the cell layout disclosed by JP-A-61-288464 after the interlayer film was formed, since the ion implantation is carried with a high energy, a code ion implanted impurity diffused region 3A (shown in FIGS. 7 and 8) becomes large in comparison with the case that, in a condition that the interlayer film has not yet been formed, the ion implantation is carried with an energy on the order of 100 kev to 150 keV. As a result, an effective channel width under an adjacent word line, namely, of an adjacent cell transistor, becomes narrow.
Now, the above mentioned influence will be described with reference to FIG. 7, which is a diagrammatic plan view for illustrating the spread of the impurity diffused region by the reference number 3A when the ion implantation is carried with the high energy in the prior art cell layout.
In FIG. 7, a cell xe2x80x9cCxe2x80x9d to be noted is shown at the same position as that shown in FIG. 5. This cell xe2x80x9cCxe2x80x9d to be noted is an on-bit cell, so that no boron ion is ion-implanted into the cell xe2x80x9cCxe2x80x9d to be noted, and on the other hand, the code ion implantation is carried out for eight cells adjacent to the on-bit cell xe2x80x9cCxe2x80x9d in eight directions. In the condition shown in FIG. 7, the influence of the adjacent cells to the on-bit cell xe2x80x9cCxe2x80x9d is the worst.
This would be seen from FIG. 8, which is a diagrammatic sectional view taken along the line Bxe2x80x94B in FIG. 7. As shown in FIG. 8, an effective channel width of the on-bit cell xe2x80x9cCxe2x80x9d is narrowed by the spread of the boron (the code ions) from an upper cell adjacent to the on-bit cell xe2x80x9cCxe2x80x9d and the spread of the boron (the code ions) from a lower cell adjacent to the on-bit cell xe2x80x9cCxe2x80x9d. As a result, the threshold of the on-bit cell xe2x80x9cCxe2x80x9d adversely becomes higher than a primarily expected threshold. This means that a reading margin of the cell in the mask ROM becomes small.
Here, it is considered to carry out the code ion implantation after the gate silicide (word line) is formed but before the interlayer film is formed, so that the code ion can be ion-implanted with a reduced energy. However, since it is strongly required to shorten a so-called TAT (turn around time) after a ROM coding data is given from a customer before a product is shipped to the customer, it is necessary to make the step of the code ion implantation as late as possible. Therefore, it is not practically acceptable to carry out the code ion implantation before the interlayer film is formed.
Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor read only memory of the flat cell structure having a large reading margin by preventing the threshold of an on-bit cell (with no code ion implantation) from becoming high because of the influence of the spread of the code ions from adjacent cells.
According to the prevent invention, there is provided a semiconductor memory wherein bit lines are formed to have a predetermined angle to word lines.
According to the prevent invention, there is also provided a semiconductor memory wherein in a region where each bit line overlaps word lines, the bit line is perpendicular to the word lines, and in a region where each bit line does not overlap the word lines, the bit line has a predetermined angle to the word lines
According to the prevent invention, there is also provided a semiconductor memory comprising:
a plurality of bit lines formed by implanting a first impurity into a first predetermined region on a semiconductor substrate;
a first oxide film formed to cover the bit lines and the semiconductor substrate;
a plurality of word lines formed of a patterned polycide film composed of a polysilicon layer deposited on the first oxide film and doped with a second impurity and a silicide layer deposited on the polysilicon layer; and
a high-threshold transistor formed by implanting code ions into a second predetermined region on the semiconductor substrate,
wherein the bit lines are formed to have a predetermined angle to the word lines.
According to the prevent invention, there is also provided a semiconductor memory comprising:
a plurality of bit lines formed by implanting a first impurity into a first predetermined region on a semiconductor substrate;
a first oxide film formed to cover the bit lines and the semiconductor substrate;
a plurality of word lines formed of a patterned polycide film composed of a polysilicon layer deposited on the first oxide film and doped with a second impurity and a silicide layer deposited on the polysilicon layer; and
a high-threshold transistor formed by implanting code ions into a second predetermined region on the semiconductor substrate,
wherein in a region where each of the bit lines overlaps the word lines, the bit line is perpendicular to the word lines, and in a region where each of the bit lines does not overlap the word lines, the bit line has the predetermined angle to the word lines.
According to the prevent invention, in the above mentioned semiconductor memories, the predetermined angle is an angle that minimizes an overlapping between a diffused region of the code ions and a region which is not implanted with the code ions and where the bit line does not overlap the word line.
According to the prevent invention, in the above mentioned semiconductor memories, the predetermined angle is an angle ensuring that a diffused region of the code ions does not overlap a region which is not implanted with the code ions and where the bit line does not overlap the word line.
According to the prevent invention, in the above mentioned semiconductor memories, the predetermined angle is 30 degrees.
According to the prevent invention, in the above mentioned semiconductor memories, the predetermined angle is an angle depicting a regular hexagon by a line which imaginarily connects respective centers of six overlapping regions of the bit lines and the word lines, all of the six overlapping regions having the same configuration and being adjacent to the same overlapping region of the bit line and the word line.
According to the prevent invention, in the above mentioned semiconductor memories, the word lines are in the form of stripes located in parallel to one another on the first oxide film formed on the semiconductor substrate.
According to the prevent invention, in the above mentioned semiconductor memories, the first predetermined region is in the form of stripes formed in the semiconductor substrate in parallel to one another and to have a predetermined width.
According to the prevent invention, in the above mentioned semiconductor memories, the second predetermined region is formed of a region in which the code ions implanted in accordance with a code to be written are diffused and which has, as its center, a center of the region which is positioned under the word line and in which the word line and the first predetermined region do not overlap each other.
According to the prevent invention, in the above mentioned semiconductor memories, the bit lines are formed of N+ diffused regions.
According to the prevent invention, the above mentioned semiconductor memory further includes an impurity diffused region of a predetermined threshold, formed by implanting a third impurity into the semiconductor substrate for controlling a threshold of a memory cell transistor.
According to the prevent invention, in the above mentioned semiconductor memories, the predetermined threshold is lower than a threshold of the high-threshold transistor.
According to the prevent invention, in the above mentioned semiconductor memories, the semiconductor substrate is a P-type silicon substrate.
According to the prevent invention, in the above mentioned semiconductor memories, the first impurity is arsenic.
According to the prevent invention, in the above mentioned semiconductor memories, the polysilicon layer is formed on the first oxide film by a chemical vapor deposition process.
According to the prevent invention, in the above mentioned semiconductor memories, the second impurity is a high concentration of phosphorus.
According to the prevent invention, in the above mentioned semiconductor memories, the silicide is a silicide of a refractory metal.
According to the prevent invention, in the above mentioned semiconductor memories, the silicide is deposited on the polysilicon layer by a sputtering.
According to the prevent invention, there is also provided a method for fabricating a semiconductor memory wherein bit lines are formed to have a predetermined angle to word lines.
According to the prevent invention, there is also provided a method for fabricating a semiconductor memory, wherein in a region where each bit line overlaps word lines, the bit line is perpendicular to the word lines, and in a region where each bit line does not overlap the word lines, the bit line has the predetermined angle to the word lines.
According to the prevent invention, there is also provided a method for fabricating a semiconductor memory comprising the steps:
implanting a first impurity into a first predetermined region on a semiconductor substrate, to form a plurality of bit lines formed of an impurity diffused region;
forming a first oxide film to cover the bit lines formed of the impurity diffused region and the semiconductor substrate;
forming a polysilicon layer on the first oxide film;
implanting a second impurity into a second predetermined region on the polysilicon layer;
forming a silicide layer on the polysilicon layer doped with the second impurity;
forming a first photoresist film having a first predetermined shape on a polycide film composed of the polysilicon layer and the silicide layer;
selectively removing the polycide film by a reactive etching using the first photoresist film as a mask, to form a plurality of word lines formed of a patterned polycide film;
removing the first photoresist film;
forming a second oxide film to cover the word lines;
forming a second photoresist film having a second predetermined shape on the second oxide film; and
implanting code ions into the semiconductor substrate by using the second photoresist film as a mask, so that a high-threshold transistor is formed by the code ions implanted in a third predetermined region that is not masked by the second photoresist film,
wherein the bit lines formed of the impurity diffused region are formed to have a predetermined angle to the word lines.
According to the prevent invention, there is also provided a method for fabricating a semiconductor memory comprising the steps:
implanting a first impurity into a first predetermined region on a semiconductor substrate, to form a plurality of bit lines formed of an impurity diffused region;
forming a first oxide film to cover the bit lines formed of the impurity diffused region and the semiconductor substrate;
forming a polysilicon layer on the first oxide film;
implanting a second impurity into a second predetermined region on the polysilicon layer;
forming a silicide layer on the polysilicon layer doped with the second impurity;
forming a first photoresist film having a first predetermined shape on a polycide film composed of the polysilicon layer and the silicide layer;
selectively removing the polycide film by a reactive etching using the first photoresist film as a mask, to form a plurality of word lines formed of a patterned polycide film;
removing the first photoresist film;
forming a second oxide film to cover the word lines;
forming a second photoresist film having a second predetermined shape on the second oxide film; and
implanting code ions into the semiconductor substrate by using the second photoresist film as a mask, so that a high-threshold transistor is formed by the code ions implanted in a third predetermined region that is not masked by the second photoresist film,
wherein in a region where each of the bit lines overlaps the word lines, the impurity diffused region constituting the bit line is formed perpendicular to the word lines, and in a region where each of the bit lines does not overlap the word lines, the impurity diffused region constituting the bit line is formed to have the predetermined angle to the word lines.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the predetermined angle is an angle that minimizes an overlapping between a diffused region of the code ions implanted by the code ion implanting step and a region which is not implanted with the code ions and where the bit line does not overlap the word line
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the predetermined angle is an angle ensuring that a diffused region of the code ions implanted by the code ion implanting step does not overlap a region which is not implanted with the code ions and where the bit line does not overlap the word line.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the predetermined angle is 30 degrees.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the predetermined angle is an angle depicting a regular hexagon by a line which imaginarily connects respective centers of six overlapping regions of the bit lines and the word lines, all of the six overlapping regions having the same configuration and being adjacent to the same overlapping region of the bit line and the word line.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the first predetermined region is formed in the form of stripes in the semiconductor substrate in parallel to one another and to have a predetermined width.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the third predetermined region is a region in which the code ions are to be implanted in accordance with a code to be written and which has, as its center, a center of the region which is positioned under the word line and in which the word line and the first predetermined region do not overlap each other.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the impurity diffused region constituting the bit lines is formed of an N+ diffused region.
According to the present invention, the above mentioned method for fabricating a semiconductor memory further includes, before the step of implanting the first impurity, the step of implanting a third impurity into the semiconductor substrate for controlling a threshold of a memory cell transistor, to form an impurity diffused region of a predetermined threshold.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the word lines are located in the form of stripes in parallel to one another on the first oxide film formed on the semiconductor substrate.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the predetermined threshold is lower than a threshold of the high-threshold transistor.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the semiconductor substrate is a P-type silicon substrate.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the first impurity is arsenic.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the polysilicon layer is formed on the first oxide film by a chemical vapor deposition process.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the second impurity is a high concentration of phosphorus.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the silicide is a silicide of a refractory metal.
According to the present invention, in the above mentioned methods for fabricating the semiconductor memory, the silicide is deposited on the polysilicon layer by a sputtering.
With the above mentioned arrangement, the cell layout is improved in accordance with the present invention to minimize the influence of the spread of the code ions implanted for the mask ROM, from a code ion implanted cell to an adjacent cell to which the code ions were not implanted.
In brief, with the above mentioned cell layout in accordance with the present invention, channel regions of memory cells are resultantly located in a checker pattern. Therefore, the influence of the spread of the code ions implanted by the code ion implantation and caused by its succeeding heat treatment, to an adjacent cell, can be minimized.
Specifically, in a flat cell type mask ROM, the influence of the code ions to the adjacent cell means that the code ions are diffused from the code ion implanted cell to an adjacent cell to which the code ions were not implanted, with the result that the threshold of the cell to which the code ions were not implanted, changes. In the case that boron is used as the impurity for the code ion implantation in the flat cell type ROM, the change of the threshold results in an elevated threshold, with the result that the reading margin becomes small. This problem has been overcome by the cell layout in accordance with the present invention.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.